- HOME
- 홈페이지 이용안내
논문 기본정보
All-Synthesizable 5-Phase Phase-Locked Loop for USB2.0
논문 개요
| 기관명 | NDSL |
|---|---|
| 저널명 | Journal of semiconductor technology and science |
| ISSN | 1598-1657, |
| ISBN |
논문저자 및 소속기관 정보
| 저자(한글) | Seong, Kihwan,Lee, Won-Cheol,Kim, Byungsub,Sim, Jae-Yoon,Park, Hong-June |
|---|---|
| 저자(영문) | |
| 소속기관 | |
| 소속기관(영문) | |
| 출판인 | |
| 간행물 번호 | |
| 발행연도 | 2016-01-01 |
| 초록 | A 5-phase phase-locked loop (PLL) for USB2.0 applications was implemented by using an all-synthesis technique. The length of the time-to-digital converter for the fine phase detector was halved by the operation of a coarse phase detector that uses 5-phase clocks. The maximum time difference between the rising edges of two adjacent-phase clocks was 6 ps at 480 MHz. The PLL chip in a 65-nm process occupies $0.038mm^2$ , consumes 4.8 mW at 1.2 V. The measured rms and peak-to-peak output jitters are 8.6 ps and 45 ps, respectively. |
| 원문URL | http://click.ndsl.kr/servlet/OpenAPIDetailView?keyValue=03553784&target=NART&cn=JAKO201620438446943 |
| 첨부파일 |
추가정보
| 과학기술표준분류 | |
|---|---|
| ICT 기술분류 | |
| DDC 분류 | |
| 주제어 (키워드) | Multi-phase,ring oscillator,digitally controlled oscillator (DCO),phase-locked loop |